In conventional electronic designs, the integrated circuits (ICs), the IC packaging, and the printed circuit boards are often developed and designed independently. Modern electronic designs often require or desire developing the integrated circuit, the their respective packaging, and the printed circuit board (PCB) incorporating multiple packaged integrated circuits in a multi-fabric environment. That is, one designer may need or desire to design in the context of the others. For example, an integrated circuit designer may need or desire to implement the integrated circuit design in view of the contexts of the packaging fabric as well as the printed circuit board fabric.
Similarly, a printed circuit board designer may need or desire to implement or tune the printed circuit design in the context of the packaging design fabric and/or the integrated circuit design fabric. As a practical example where an advanced package is to be integrated into a printed circuit board (PCB) for an electronic product that is driven by cost considerations and performance. In conventional approaches, while device placement and assignment decisions made solely in the context of the chip may yield the ideal chip-level design, these device placement and assignment decisions could nevertheless result in missing the cost or performance goals for the end consumer product. In these convention approaches, the chip-level placement usually dictates, for example, the bump and ball assignments in the downstream fabrics that may result in excessive coupling in, for example, the interfaces and a complex routing scheme that requires additional layers in the package and/or PCB substrates.
A power distribution network (or power delivery network or PDN) includes the circuit components, traces, and/or metal structures that deliver power not only to the device under test but also to various other devices in an entire electronic design including one or more packaged integrated circuits, cells, discrete circuit components, and traces. Although early rail analyses and power grid implementations and optimizations may provide reasonably accurate results, IC packages and the printed circuit board itself may often cause additional drop in the power distribution network before the supplied power enters the power grid of integrated circuits or cells.
Furthermore, a power distribution network for a system under test may be loaded by the entire system, and such a load by the entire system may impact power delivery to individual integrated circuits and cells. Conventional I/O (input/output) drop analyses often assume an ideal voltage on all the power pads of an integrated circuit. This assumption is far from reality where voltages on different power pads of an integrated circuit may not necessarily be the same, much less having the same ideal voltage, due to, for example, lack of system symmetry, the dissipation within the power distribution network, consumption by other circuit components, etc.
With mixed-signal electronic designs, the voltage drop (IR drop) of an analog block or die needs system driven simulations. This system driven simulation that needs the visibility of the complete circuit of at least the analog block or die is in sharp contrast with digital dies or cells that may operate and be analyzed with test vectors. Conventional approaches require manual construction of the system under test to simulate the system including analog or mixed-signal dies. Some of these approaches also perform a single analog die electro-migration and/or IR-drop (EMIR) analysis by assuming ideal voltages at the pads of the single analog or mixed-signal die and require manual stitching between, for example, an IC package and the PDN model interface for the analog die. For example, conventional approaches require manual stitching between the Vdd pad of an IC die and the corresponding supply in the PDN model. These approaches often fail to accommodate the power consumption or dissipation of the package—PCB interface power distribution network in the power consumption or dissipation of the entire system. Moreover, these conventional approach are often, if not always, performed at non-schematic levels.
In addition to the imprecise or inaccurate power consumption and/or power dissipation results, conventional thermal analyses of a system often do not account for Joule heating of surrounding circuit components. Some approaches even use power dissipation data of various circuit components from data sheets that are generated for worst-case scenarios. Some approaches uses root mean square (RMS) or average power dissipation data and thus cannot capture transient or instantaneous thermal behavior. Many conventional approaches also fail to account for capacitances and inductors in thermal analyses.
Therefore, there exists a need for methods and apparatuses for implementing a multi-fabric mixed-signal electronic design spanning across multiple design fabrics with electrical and thermal analysis awareness.